(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to define a polysilicon gate structure for a metal oxide semiconductor field effect transistor (MOSFET) device.
(2) Description of Prior Art
Micro-miniaturization, or the ability to fabricate semiconductor devices with sub-micron features, has allowed the performance of the sub-micron device to be increased while the fabrication cost of the same sub-micron semiconductor device has been decreased. The smaller device features result in decreases in performance degrading parasitic capacitances in addition to allowing a greater number of smaller semiconductor chips, still comprised with device densities comparable to larger semiconductor chips, to be obtained from a specific size starting wafer thus reducing the process cost of each individual semiconductor chip. One critical dimension of sub micron semiconductor or MOSFET devices, is the width of the conductive gate structure, or the channel length of the MOSFET device. This dimension is critical in determining MOSFET device performance. Conductive gate structures defined in polysilicon layers via photoresist masking and dry etching procedures, have been used to define narrow width conductive gate structures. However to control this critical dimension anti-reflective coatings (ARC), layers are employed underlying the masking photoresist shape to optimize photoresist exposure and thus optimize the definition of the polysilicon gate structure using the narrow photoresist shape as an etch mask. To further insure critical dimension control of the masking photoresist shape a dual ARC strategy is used. The dual ARC technology comprises a bottom anti-reflective coating (BARC), layer underlying the pre-exposed photoresist layer and a dielectric anti-reflective coating (DARC), layer underlying the BARC layer, with the DARC layer sometimes comprised of silicon nitride or silicon oxynitride. After definition of the conductive gate structure removal of the DARC layer is accomplished using a hot phosphoric acid solution capitalizing on the high selectivity between the fast etching silicon nitride or silicon oxynitride DARC layer and underlying non-silicon oxide materials. However the hot phosphoric wet etch tanks if not frequently maintained can be loaded with unwanted particles as a result of previous applications. After DARC removal particles from the contaminated hot phosphoric acid wet etch tank can deposit on critical regions of the in-process MOSFET device resulting in yield loss.
The present invention will describe a procedure for defining a MOSFET device conductive gate structure, wherein a dual ARC technology is used. However this invention will teach removal of a DARC layer without employment of hot phosphoric acid thus avoiding the contamination and possible yield detractors resulting from unwanted particles in the hot phosphoric acid. Prior art such as Yang et al in U.S. Pat. No. 6,579,809 B1, Yu et al in U.S. Pat. No. 6,403,432 B1, and Tao et al in U.S. Pat. No. 6,524,938 B1, describe process sequences in which ARC or BARC layers are employed in defining polysilicon gate structures for MOSFET devices, however the above prior art do not describe the process sequence described in the present invention in which a dual ARC layer is used for critical dimension control and wherein a non-phosphoric acid procedure is used to remove dual ARC components.